1. Field of the Invention
Embodiments of the present invention relate to DC offset reduction techniques for differential signals, and, in particular, to DC offset reduction techniques for signal handling elements such as amplifiers, mixers and current mode down converters.
2. Description of Related Art
The performance of an electronic device depends on the performance of the individual elements that constitute the device. For example, the performance of electronic devices such as cellular telephones, personal digital assistants and other wireless and wired devices depend heavily on the performance of the various signal handling elements of the device. The output provided by each element influences the performance of each subsequent element. Consequently, the quality of the output signal produced by an element can be critical to the performance of the device in general.
One goal of circuits that use differential signals is to minimize any DC offset in the output signals. DC offset may be eliminated using a feedback loop, however feedback loops are complex and consume significant space and power. As an alternative, an open loop DC offset compensation circuit may be utilized in the output stage. FIG. 1 shows a circuit level diagram of a conventional current mode output stage circuit for supplying differential output signals. An input signal Iin composed of a DC bias component IDC1 and a signal component Isig is received at a first input 10, and a complementary input signal −Iin composed of a DC bias component IDC2 and a complementary signal component −Isig is received at an input 18. Ideally the DC bias components IDC1 and IDC2 of the input signals are equal. Any difference between the DC bias components is referred to as DC offset.
In the output stage circuit of FIG. 1, the input signal Iin is provided to a reference PMOS transistor 12 that is coupled to the input 10. Current in the reference transistor 12 is mirrored in a mirror transistor 14 that has its gate coupled to the gate of the reference transistor 12, and the mirror current is supplied to an output 16. The complementary input signal −Iin is provided to a reference PMOS transistor 20 that is coupled to the input 18. Current in the reference transistor 20 is mirrored in a mirror transistor 22 that has its gate coupled to the gate of the reference transistor 20, and the mirror current is supplied an output 24. The reference transistors 12, 20 and the mirror transistors 14, 22 are implemented as matched pairs.
The ideal output stage circuit supplies the signal components of the input signals to the outputs without DC bias or DC offset. In the conventional output stage circuit of FIG. 1, DC bias is removed by bias transistors 26, 28 that are coupled to the output nodes 16, 24 to supply DC counter-bias currents. The amount of current supplied by each bias transistor is controlled by respective bias control voltages Vbias1, Vbias2 supplied to the gates 30, 32 of the bias transistors 26, 28.
It is difficult to approximate ideal operation with the conventional output stage circuit of FIG. 1. The bias control voltages Vbias1, Vbias2 are typically set once for the circuit, and cannot be adjusted to compensate for any DC offset that occurs in the input signals. Since the counter-bias currents supplied by the PMOS bias transistors 26, 28 will only match the bias currents of the NMOS mirror transistors 14, 22 at limited process, temperature and voltage conditions, the circuit is very sensitive to a number of factors including the properties of the individual transistors and changes in the DC bias components of the input signals, and therefore is only somewhat effective for removing DC offset.